The present invention disclosed herein relates to a discharge circuit for discharging two positive and negative high voltages after an erase operation of a non-volatile memory.
FIG. 8 is a cross-sectional structure of a flash memory cell and illustrates an electric potential state during an erase operation. In FIG. 8, coupling parasitic capacitance Cp, which causes various limitations during resetting of a voltage after an erase operation of a flash memory cell, also is illustrated. In the flash memory cell of FIG. 8, an N-well 12 and a P-well 13 are formed in a P-type substrate 11, and a source/drain region 14 of the memory cell is formed in the P-well 13. Moreover, a floating gate 15 and a control gate 16 are stacked on the P-well 13 between the source region 14 and the drain region 14. The control gate 16 is connected to a word line WL. Coupling parasitic capacitance Cp is formed between the word line WL and the P-well 13.
In a typical NOR flash memory having the above flash memory cell, a negative high voltage (e.g., −9 V, hereinafter, referred to as Vneg) supplied from a charge pump is applied to the word line WL and a positive high voltage (e.g., 9 V, hereinafter, referred to as Vpm) supplied from another charge pump is applied to the wells 12 and 13, during a data erasing operation. Therefore, electrons in the floating gate 15 transfers to the wells 12 and 13 through an FN tunneling phenomenon in order to erase stored data. Although physical one bit cell is illustrated in FIG. 8, the erasing of stored data is completed by a large block unit such that a voltage Vneg is simultaneously applied to a plurality of word lines WL. Accordingly, an overall coupling parasitic capacitance Cp between the word lines WL and the P-well is increased. This coupling parasitic capacitance Cp causes coupling noise during the resetting of a voltage after an erase operation.
A detailed description of the above limitation is disclosed in U.S. Pat. No. 6,373,749 and this will be described in brief. FIGS. 9 through 11 are timing charts illustrating the above limitations. FIG. 9 is a timing chart when voltages Vneg and Vpm are not simultaneously reset and the voltage Vneg is reset first. Japanese Patent Publication No. 2005-310301 uses the above timing chart. In this timing chart, since about −9 V is discharged at about 0 V, voltage amplitude changes significantly and its noise increases a voltage Vpm having a floating state through the coupling parasitic capacitance Cp. Accordingly, since the voltage Vpm, which originally has a high voltage, is increased more by the noise, it may exceed a withstanding voltage of a transistor in a decoder circuit that supplies the voltage Vpm. This may cause physical damage in the transistor. As a result, defective chip can be produced.
FIG. 10 is a view when a voltage Vpm is reset first. Due to the same reason, a voltage Vneg exceeds a withstanding voltage. Therefore, same risk may occur as before.
FIG. 11 is a view when voltages Vpm and Vneg are reset simultaneously. In this case, when considering reset capability of voltages Vpm and Vneg, noise may differently occur. In FIG. 11, transistor's capability for resetting the voltage Vpm is higher than that of the voltage Vneg. The voltage Vpm is reset fast and the voltage Vneg is reset slowly. Thus, noise from the voltage Vpm becomes greater than reset such that the Vneg may exceed a withstanding voltage.